The present invention relates to a layout of a semiconductor device.
Generally, a semiconductor device forms two transistors in one active region using an active region of I-type or G-type, so that it results in a “one active region and two capacitors therein” structure. However, the “one active region and two capacitors therein” structure encounters a bridge problem between neighboring patterns so that it unavoidably deteriorates characteristics of a semiconductor device. In more detail, with the increasing degree of integration of a semiconductor device, higher-aspect-ratio patterns are laminated in the semiconductor device. In this case, some patterns fall down so that they bridge neighboring patterns, resulting in a deterioration of characteristics of the semiconductor device. In brief, this problem is generally referred to as a bridge problem.
FIG. 1 is a plan view illustrating the layout of a semiconductor device according to the related art. FIGS. 2A to 2D are cross-sectional views illustrating a method for forming a semiconductor device according to the related art.
Referring to FIG. 1, an active region 14, a word line 16, landing plugs 22a and 22b, a bit line contact 26, a bit line 27, and a storage electrode contact (not shown) are formed on a semiconductor substrate 10. The active region 14 is defined by a device isolation region 12. The word line 16 vertically traverses the active region 14 to be trisected. The landing plugs 22a and 22b are formed on each trisected active region 14. The bit line contact 26 is connected to the landing plug 22a located at the center of the trisected active region 14, and is arranged in parallel to the word line 16. The bit line 27 is connected to the bit line contact 26, and is arranged perpendicular to the word lines 16. The storage electrode contact (not shown) is connected to the trisected landing plugs 22b. For convenience of explanation, detailed description of the layout of the conventional semiconductor device will be limited only up to the storage electrode contacts (not shown).
Referring to FIG. 2A, an active region 14 defined by a device isolation region 12 is formed on a semiconductor substrate 10, and a conductive layer and a hard mask layer are deposited on the active region 14 and then patterned, so that the word line 16 including a spacer 18 is formed on the active region 14.
Referring to FIG. 2B, after an interlayer insulating layer 20 is formed on an overall upper surface including the word line 16, and then selectively removed to form a recess and expose the active region 14. Then, conductive material is filled in the recess and contacts the exposed active region 14 to form landing plugs 22a and 22b. In this case, if the spacer formed at the sidewalls of the word line is removed due to misalignment, the word line 16 becomes electrically connected with the landing plugs 22a or 22b, and thus an electrical short may occur. In this case, the landing plugs are classified into one landing plug 22a connected to a bit line and another landing plug 22b connected to a storage electrode.
Referring to FIG. 2C, a first interlayer insulating layer 24 is formed on the overall structure including the landing plugs 22a and 22b, and selectively etched to expose the landing plug 22a to form a bit line contact region. Then, conductive material is filled in the bit line contact region to form a bit line contact 26. Even in this step, there is a possibility that the bit line contact 26 and the word line 16 are electrically connected due to misalignment. Thereafter, a bit line (not shown) is formed to be in contact with the bit line contact 26.
Referring to FIG. 2D, a second interlayer insulating layer 28 is formed on an overall upper surface, and the first and second interlayer insulating layers 24, 28 are selectively etched to expose the landing plug 22b. Conductive material is formed on the exposed landing plug 22b to form a storage electrode contact 30.
The conventional semiconductor device having the above-mentioned layout structure has a disadvantage in that an electrical short occurs easily due to misalignment. In addition, as the distance between neighboring layers becomes shorter as a semiconductor device shrinks in size.